1. Technical Field
The present invention relates to a semiconductor circuit technology, and more particularly, to a duty correction circuit.
2. Related Art
In a semiconductor circuit technology, e.g., a semiconductor memory apparatus, internal circuits operate in synchronization with an external clock signal.
It is ideal that a duty rate of a clock signal is 50%, that is, a high pulse duration is equal to a low pulse duration.
However, an error may occur in a duty rate of a clock signal when malfunction of a clock signal generator or failure of a signal transmission line occurs.
Consequently, there is a need for technology which can compensate a duty rate error of a clock signal inside a device which uses the clock signal, even though an error exists in a duty rate of an external clock signal.